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12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer ics85352i idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 1 ics85352ayi rev b september 27, 2006 b lock d iagram p in a ssignment g eneral d escription the ics85352i is a 12 bit, 2-to-1 lvpecl multi- plexer and is a member of the hiperclocks tm family of high performance clock solutions from idt. individual input select controls support independent multiplexer operation from a common clock input source. clock inputs accept most standard differential levels. the ics85352i is characterized at full 3.3v or mixed 3.3v core/2.5v output operating supply modes. f eatures ? twelve, 2-to-1 multiplexers with lvpecl outputs ? selectable differential clkx, nclkx input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 700mhz ? individual select control for each multiplexer ? select inputs accept lvcmos / lvttl levels ? propagation delay: 1.8ns (maximum) ? full 3.3v or mixed 3.3v core/2.5v output supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 q8 nq8 q9 nq9 q10 nq10 q11 nq11 v cco v ee v cc sel11 sel10 sel9 sel3 sel4 sel5 v cc v ee v cco ics85352i v cco clk1 nclk1 sel8 sel7 sel6 sel0 sel1 sel2 clk0 nclk0 v cco 48-lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view 0 1 0 1 12 sel0:sel11 clk0 nclk0 clk1 nclk1 q0 nq0 q11 nq11
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 2 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t able 2. p in c haracteristics t able 1. p in d escriptions t able 3. c ontrol i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1 4 , 3 6 , 5 8 , 7 0 1 , 9 2 1 , 1 1 6 2 , 5 2 8 2 , 7 2 0 3 , 9 2 2 3 , 1 3 4 3 , 3 3 6 3 , 5 3 0 q n , 0 q 1 q n , 1 q 2 q n , 2 q 3 q n , 3 q 4 q n , 4 q 5 q n , 5 q 1 1 q , 1 1 q n 0 1 q , 0 1 q n 9 q , 9 q n 8 q , 8 q n 7 q , 7 q n 6 q , 6 q n t u p t u o. s l e v e l e c a f r e t n i l c e p v l . s r i a p t u p t u o l a i t n e r e f f i d , 4 2 , 3 1 8 4 , 7 3 v o c c r e w o p. s n i p y l p p u s t u p t u o 3 2 , 4 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 2 2 , 5 1v c c r e w o p. s n i p y l p p u s e v i t i s o p , 7 1 , 6 1 , 9 1 , 8 1 , 1 2 , 0 2 , 1 4 , 0 4 , 3 4 , 2 4 5 4 , 4 4 , 4 l e s , 5 l e s , 9 l e s , 3 l e s , 1 1 l e s , 0 1 l e s , 7 l e s , 8 l e s , 0 l e s , 6 l e s 2 l e s , 1 l e s t u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i t c e l e s k c o l c 8 31 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 9 31 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 6 40 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7 40 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? x l e ss t u p n i k c o l c d e t c e l e s 00 k l c n , 0 k l c 11 k l c n , 1 k l c
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 3 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v 5%, v cco = 2.5v to 3.3v 5%, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v cc = 3.3v 5%, v cco = 2.5v to 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c , 0 k l cv c c v = n i v 5 6 4 . 3 =0 5 1a 1 k l c n , 0 k l c nv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c , 0 k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a 1 k l c n , 0 k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v k a e p - o t - k a e p 5 1 . 00 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v t u p n i e d o m n o m m o c : 1 e t o n h i . v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i1 1 l e s : 0 l e s2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i1 1 l e s : 0 l e s3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i1 1 l e s , 0 l e sv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i1 1 l e s , 0 l e sv c c v , v 5 6 4 . 3 = n i v 0 =5 -a a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 27.6c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v 5%, v cco = 2.5v to 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 23 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 7 1a m
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 4 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t able 5b. ac c haracteristics , v cc = 3.3v5%, v cco = 2.5v5%, t a = -40c to 85c t able 5a. ac c haracteristics , v cc = v cco = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 . 15 . 10 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 8 1s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 7s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 10 0 7s p c d oe l c y c y t u d t u p t u of z h m 2 2 65 45 5% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 4d. lvpecl dc c haracteristics , v cc = 3.3v 5%, v cco = 2.5v to 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 . 15 . 10 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 8 1s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 7s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 10 0 7s p c d oe l c y c y t u d t u p t u of z h m 2 2 65 45 5% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 5 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer p arameter m easurement i nformation d ifferential i nput l evel scope qx nqx lvpecl 3.3v c ore /2.5v o utput l oad ac t est c ircuit 2.8v 0.04v v cco -0.5v 0.125v v cc 2v 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.165v p art - to -p art s kew o utput s kew v cmr cross points v pp v ee clkx nclkx v cc t sk(o) qx qy nqx nqy v cc , v cco v ee v ee t sk(pp) part 1 qx qy nqx nqy part 2 o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v swing o utput d uty c ycle /p ulse w idth /p eriod p ropagation d elay clkx t pd t pw t period t pw t period odc = x 100% qx nclkx nqx qx nqx
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 6 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vcc i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 7 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 2a. h i p er c lock s clk/nclk i nput d riven by idt h i p er c lock s lvhstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 8 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination exposed pad expose metal pad (ground pad) ground plane solder signal trace signal trace thermal via solder mask f igure 3. p.c. b oard for e xposed p ad t hermal r elease p ath e xample t hermal r elease p ath the expose metal pad provides heat transfer from the device to the p.c. board. the expose metal pad is ground pad connected to ground plane through thermal via. the exposed pad on the device to the exposed metal pad on the pcb is contacted through solder as shown in figure 6. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology.
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 9 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 5b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 10 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer a pplication s chematic e xample figure 6 shows an example of ics85352i application schematic. in this example, the device is operated at v cc =3.3v the decoupling capacitor should be located as close as possible to the power pin. for the lvpecl output drivers, only two r4 133 clk0 r2 50 zo = 50 sel5 sel1 sel9 (u1-15) + - (u1-48) vcc0 c7 .1uf c3 .1uf (u1-13) optional termination sel10 c4 .1uf vcc = vcco = 3.3v c5 .1uf sel0 sel7 vcco = 3.3v (u1-22) r5 82.5 (u1-24) c2 0.1uf c1 10uf u1 85352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 vcco vee vcc sel5 sel4 sel3 sel9 sel10 sel11 vcc vee vcco q6 nq6 q7 nq7 q8 nq8 q9 nq9 q10 nq10 q11 nq11 vcco nclk0 clk0 sel2 sel1 sel0 sel6 sel7 sel8 nclk1 clk1 vcco sel2 zo = 50 sel6 c6 .1uf r6 133 + - clk1 nclk1 r3 50 r7 82.5 zo = 50 r1 50 sel11 zo = 50 (u1-37) sel4 sel3 sel8 nclk0 vcc c1 10uf terminations examples are shown in this schematic. additional termination approaches can be found in the lvpecl termination application note. f igure 6. ics85352i a pplication s chematic
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 11 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85352i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85352i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 170ma = 589.1mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 12 * 30mw = 360mw total power _max (3.465v, with all outputs switching) = 589.1mw + 360mw = 949.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 22.6c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.949w * 22.6c/w = 106.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 27.6c/w 22.6c/w 20.7c/w t able 6. t hermal r esistance ja for 48- pin tqfp, f orced c onvection
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 12 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco - 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 7. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 13 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer r eliability i nformation t ransistor c ount the transistor count for ics85352i is: 2252 t able 7. ja vs . a ir f low t able for 48 l ead tqfp, e-p ad ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 27.6c/w 22.6c/w 20.7c/w
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 14 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 rev. a p ackage o utline - y s uffix for 48l tqfp, e-pad -hd version heat slug down n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s d h - c b a m m i n i ml a n i m o nm m i x a m n 8 4 a - -- -0 2 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 9 . 00 0 . 15 0 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d c i s a b 0 0 . 4 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e c i s a b 0 0 . 4 e c i s a b 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c - -- -8 0 . 0 3 e & 3 d 0 . 20 . 7
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 15 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i y a 2 5 3 5 8 s c ii y a 2 5 3 5 8 s c id a p - e , p f q t d a e l 8 4y a r tc 5 8 o t c 0 4 - t i y a 2 5 3 5 8 s c ii y a 2 5 3 5 8 s c id a p - e , p f q t d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l i y a 2 5 3 5 8 s c il i y a 2 5 3 5 8 s c id a p - e , p f q t " e e r f - d a e l " d a e l 8 4y a r tc 5 8 o t c 0 4 - t f l i y a 2 5 3 5 8 s c il i y a 2 5 3 5 8 s c id a p - e , p f q t " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
idt ? / ics ? 3.3v, 2.5v lvpecl clock multiplexer 16 ics85352ayi rev b september 27, 2006 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 9 t 1 6 7 5 1 . t e t l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d e d d a . h t a p e s a e l e r l a m r e h t . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 6 / 7 b a 4 t3 v d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c d y l p p u s r e w o p c c o t v 5 7 4 . 3 m o r f . n i m . v 5 3 1 . 3 6 0 7 2 / 9
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ics85352i 12 bit, 2-to-1, 3.3v, 2.5v lvpecl clock multiplexer ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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